1. Technical Field
Embodiments described herein relate generally to a semiconductor memory apparatus and, more particularly, to a clock signal generating circuit and a semiconductor memory apparatus including the same.
2. Background
A typical semiconductor memory apparatus is configured to receive an external clock signal and generate an internal clock signal having a phase locked through a delay locked loop circuit so that the internal clock signal operates in synchronization with the external clock signal. Further, the semiconductor memory apparatus generates a pair of clock signals having a 180 degree phase difference for high-speed operation and operates in synchronization with the phase difference.
FIG. 1 is a block diagram schematically showing a configuration of a conventional clock signal generating circuit. In FIG. 1, the clock signal generating circuit includes a delay locked loop circuit (hereinafter, referred to as ‘DLL circuit’) 10, a main clock buffer 20, and a sub clock buffer 30. The DLL circuit 10 generates first and second delay clock signals ‘irclkdll’ and ‘ifclkdll’ using a received external clock signal ‘CLK’. The main clock buffer 20 generates first and second internal clock signals ‘rclkdll’ and ‘fclkdll’ by buffering the first and second delay clock signals ‘irclkdll’ and ‘ifclkdll’. The first and second sub clock buffer 30 generates first and second clock signals ‘rclk’ and ‘fclk’ by buffering the first and second internal clock signals ‘rclkdll’ and ‘fclkdll’, respectively. The first and second clock signals ‘rclk’ and ‘fclk’ are transmitted to circuits that operate in synchronization with the clock signals.
As described above, the clock generating circuit includes buffers receiving and buffering clock signals. The buffering operation of the buffers allow a differential clock pair to be generated irrespective of frequency variations of the clock signals. In operation, the main clock buffer 10 is at all times operating in order to buffer the first and second delay clock signals ‘irclkdll’ and ‘ifclkdll’ and generate the first and second internal clock signals ‘rclkdll’ and ‘fclkdll’. A consequence of the continuous operation of the main clock buffer is increased power consumption.